Zishen Wan  

I am a second-year Ph.D. student at Georgia Tech, advised by Prof. Arijit Raychowdhury at Integrated Circuits and Systems Research Lab. I am particularly interested in computer architecture, VLSI design, and robotics.

Before coming to Georgia Tech, I received my M.S. in Electrical Engineering from Harvard University in 2020. During my master, I was fortunate to be advised by Prof. Vijay Janapa Reddi at Edge Computing Lab, and collaborated with Prof. David Brooks and Prof. Gu-Yeon Wei at VLSI-Arch Lab.

I received my B.Eng. in Electrical Engineering from Harbin Institute of Technology in 2018. During my undergrad, I was fortunate to work with Prof. Dianguo Xu and Prof. Xueguang Zhang.

I was a cross-registered student at MIT from 2018 to 2020, and a visiting student at National Chiao-Tung University and National Tsing-Hua University in 2017.

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                  Email:
                  zishenwan@gatech.edu
News

Book
Robotic Computing on FPGAs
Shaoshan Liu, Zishen Wan, Bo Yu, Yu Wang
Editor: Natalie Enright Jerger
Synthesis Lectures on Computer Architecture (Morgan & Claypool Publishers), pp.1-218, Jun 2021
Book / Bibtex

This book provides a thorough overview of the state-of-the-art FPGA-based robotic computing accelerator designs and summarizes their adopted optimized techniques. This book consists of ten chapters, delving into the details of how FPGAs have been utilized in robotic perception, localization, planning, and multi-robot collaboration tasks. In addition to individual robotic tasks, this book provides detailed descriptions of how FPGAs have been used in robotic products, including commercial autonomous vehicles and space exploration robots. Some key observations of this book has been published as a survey paper in IEEE Circuits and Systems Magazine, 2021.

Publications [Full List]       (*: Equal Contributions)
Analyzing and Improving Fault Tolerance of Learning-Based Navigation System
Zishen Wan, Aqeel Anwar, Yu-Shun Hsiao, Tianyu Jia, Vijay Janapa Reddi, Arijit Raychowdhury
ACM/IEEE Design Automation Conference (DAC), 2021
Paper / Bibtex

We evaluate the resilience of learning-based navigation systems to transient and permanent hardware faults. We further propose two efficient fault mitigation techniques for both RL training and inference.

MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles
Yu-Shun Hsiao*, Zishen Wan*, Tianyu Jia, Radhika Ghosal, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi (*Equal contributions with alphabetical order)
Pre-print, 2021
Paper / Code / Bibtex

We build a ROS-based end-to-end fault analysis framework to understand the resilience of Micro Aerial Vehicles (MAVs) system, and propose two low overhead anomaly-based transient fault detection and recovery schemes.

An Energy-Efficient Quad-Camera Visual System for Autonomous Machines on FPGA Platform
Zishen Wan*, Yuyang Zhang*, Arijit Raychowdhury, Bo Yu, Yanjun Zhang, Shaoshan Liu
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021
Paper / Bibtex

We present a real-time and energy-efficient ORB (Oriented-Fast and Rotated-BRIEF) based visual system on FPGAs. Compared to Nvidia TX1 and Intel i7 CPU, our FPGA-based implementation achieves 5.6x and 3.4x speedup, as well as 3.0x and 34.6x power reduction, respectively.

iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform
Tian Gao*, Zishen Wan*, Yuyang Zhang, Bo Yu, Yanjun Zhang, Shaoshan Liu, Arijit Raychowdhury
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021
Paper / Bibtex

We present an energy-efficient hardware architecture for real-time ELAS (Efficient Large-scale Stereo) based stereo matching on FPGAs. Compared to SOTA SoC and Intel i7 CPU, our FPGA design achieves 3.32x and 38.4x speedup, and 1.13x and 27.1x power reduction, respectively.

AutoSoC: Automating Algorithm-SoC Co-design for Aerial Robots
Srivatsan Krishnan, Thierry Tambe, Zishen Wan, Vijay Janapa Reddi
Pre-print, 2021
Paper / Poster / Bibtex

We present AutoSoC, a algorithms-hardware co-design framework for end-to-end learning-based aerial autonomous machines. AutoSoC runs the ASIC flow of place and route and generates layouts of the floor-planed accelerators with varying performance, area, and power consumption.

AutoPilot: Automating SoC Design Space Exploration for SWaP Constrained Autonomous UAVs
Srivatsan Krishnan, Zishen Wan, Kshitij Bhardwaj, Paul Whatmough, Aleksandra Faust, Sabrina M. Neuman, Gu-Yeon Wei, David Brooks, Vijay Janapa Reddi
Pre-print, 2021
Paper / Bibtex

We propose a machine learning-based design space exploration framework, Autopilot, that can automate the full system cyber-physical co-design for aerial robots. AutoPilot consistently outperforms general-purpose processors and specialized accelerators built for drones.

A Survey of FPGA-Based Robotic Computing
Zishen Wan*, Bo Yu*, Thomas Yuang Li, Jie Tang, Yuhao Zhu, Yu Wang, Arijit Raychowdhury, Shaoshan Liu
IEEE Circuits and Systems Magazine (CAS-M), 2021
Paper / arXiv / Bibtex

We provide an overview of recent work on FPGA-based robotic accelerators. An analysis of software and hardware optimization techniques and main technical issues is presented, along with some commercial and space applications.

(Gif source: Google)
ActorQ: Quantization for Actor-Learner Distributed Reinforcement Learning
Max Lam*, Sharad Chitlangian*, Srivatsan Krishnan*, Zishen Wan, Gabriel Barth-Maron, Aleksandra Faust, Vijay Janapa Reddi
International Conference on Learning Representations (ICLR) HEAT Workshop, 2021
Paper / Code

We introduce a novel Reinforcement Learning training paradigm, ActorQ, to speed up actor-learner distributed RL training. ActorQ demonstrates >1.5x-2.5× speedup, and faster convergence over full precision training on a range of tasks (Deepmind Control Suite) and RL algorithms (D4PG, DQN).

Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference
Thierry Tambe, En-Yu Yang, Zishen Wan, Yuntian Deng, Vijay Janapa Reddi, Alexander Rush, David Brooks, Gu-Yeon Wei
ACM/IEEE Design Automation Conference (DAC), 2020   (Best Paper Award)
Paper / arXiv (long version) / Bibtex

We present an algorithm-hardware co-design centered around a novel floating-point inspired number format, which can achieve higher inference accuracies and lower per-operation energy compared to NVDLA-like PE.

The Sky Is Not the Limit: A Visual Performance Model for Cyber-Physical Co-Design in Autonomous Machines
Srivatsan Krishnan, Zishen Wan, Kshitij Bhardwaj, Paul Whatmough, Aleksandra Faust, Gu-Yeon Wei, David Brooks, Vijay Janapa Reddi
IEEE Computer Architecture Letters (CAL), 2020   (Best Paper Award)
Presented at International Symposium on High-Performance Computer Architecture (HPCA), 2021
Paper / Tool Website / Bibtex

We introduce a roofline-like model to understand the role of computing in aerial autonomous machines. The model provides insights by exploiting the fundamental relationships between various components in an aerial robot, such as sensor framerate, compute performance, and body dynamics.

Quantized Reinforcement Learning (QuaRL)
Srivatsan Krishnan*, Sharad Chitlangian*, Max Lam*, Zishen Wan, Aleksandra Faust, Vijay Janapa Reddi
Conference on Machine Learning and System (MLSys) ReCoML Workshop, 2020
Paper / arXiv (long version) / Code / Bibtex

We conduct the first comprehensive empirical study that quantifies the effects of quantization on various deep RL tasks and algorithms. We deploy a quantized RL-based robot navigation policy onto an embedded system, achieving 18x speedup and 4x reduction in memory usage.

Electrically tunable temporal imaging in a graphene-based waveguide
Peng Xie, Yu Wen, Zishen Wan, Xinyu Wang, Jiarui Liu, Wenqiang Yang, Xiaofeng Li, Yishan Wang
Japanese Journal of Applied Physics, 2019
Paper / Bibtex

Simplified Implementation of Optimal Switching Sequences for Nonorthogonal Space Vector Modulation of Three Level Converter
Weiwei Li, Xueguang Zhang, ​​​​​​​Zishen Wan, Yini Zhao, and Dianguo Xu
Transactions of China Electrotechnical Society, 34, Pp. 181-188, 2019
Paper / Bibtex

Influences of Group Velocity Dispersion on Ultrafast Pulse Shaping in Time Lens
Peng Xie, Yu Wen, Zishen Wan, and Yishan Wang
Physica Scripta, 94(12):125503, 2019
Paper / Bibtex

Tunable Gallium Nitride-based Devices for Ultrafast Signal Processing
Peng Xie, Yu Wen, Wenqiang Yang, Zishen Wan, Jiarui Liu, Xinyu Wang, Siqi Da, and Yishan Wang
Modern Physics Letters B, 33(17), 2019
Paper / Bibtex

Modulation and Neutral Voltage Balance Control of NPC Three-level Converter
Zishen Wan
Undergraduate Thesis, 2018   (Best Undergraduate Thesis Award of Harbin Institute of Technology)
Full Paper / Short Paper
Honors and Awards

  • 2021 Young Student Fellow, IEEE/ACM Design Automation Conference (DAC)
  • 2020 Best Paper Award, IEEE/ACM Design Automation Conference (DAC)
  • 2020 Best Paper Award, IEEE Computer Architecture Letters (CAL)
  • 2018 Chiang Chen Overseas Graduate Scholarship (10 of all undergraduates and graduates in China)
  • 2018 Best Undergraduate Thesis Award
  • 2018 Frist Place, Chunhui Innovation Achievement Award (Highest Student Academic Honor of HIT)
  • 2018 Top Ten Outstanding Undergraduates of HIT
  • 2018 China Telecom Scholarship
  • 2017 Innovation and Entrepreneurship Award, Ministry of Industry and Information, China
  • 2016 First Place, National Mathematical Contest in Modeling, China
  • 2016 Siemens Acedemic Scholarship
  • 2015 Johnson Electric Acedemic Scholarship
Talks

  • 2021 Enabling Reliable and Safe Autonomous Navigation Systems
  • 2020 Edge Computing on Aerial Robots
  • 2020 Micro Aerial Vehicle Fault Injection and Detection
Misc

  • Sports: I like table tennis, soccer, and swimming. I'm a member of Georgia Tech Table Tennis Association (GTTTA).
  • Arts: I like calligraphy and have practiced more than 10 years. My undergrad Calculus class notes was awarded 'The Most Beautiful Class Note' and permanently collected and displayed by university museum.

Last Update: Oct. 2021

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