Zishen Wan  

I am a 4th-year Ph.D. student at Georgia Tech, advised by Prof. Arijit Raychowdhury and Prof. Tushar Krishna. I also closely work with Prof. Vijay Janapa Reddi. My research interests are in computer architecture and VLSI, with a focus on designing efficient and reliable hardware and systems for autonomous machines and cognitive intelligence.

I received M.S. from Harvard University where I was fortunate to be advised by Prof. Vijay Janapa Reddi, and collaborated with Prof. David Brooks and Prof. Gu-Yeon Wei. I received B.Eng. from Harbin Institute of Technology. I was a visiting student at MIT CSAIL, National Chiao Tung University, and National Tsing Hua University.

I commit 1 hour every week to provide guidance, suggestions, and/or mentorships for students from underrepresented groups or whoever is in need. Please fill in this form if you are interested.

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                  Email:
                  zishenwan@gatech.edu
Research Interests

My research is at the intersection of VLSI, computer architecture, and embedded system. I build hardware and system for autonomous machines and cognitive intelligence, with the vision to advance their performance, efficiency, resilience, and trustworthy.
News

Books
Robotic Computing on FPGAs
Shaoshan Liu, Zishen Wan, Bo Yu, Yu Wang
Editor: Natalie Enright Jerger
Synthesis Lectures on Computer Architecture (Morgan & Claypool Publishers), pp.1-218, Jun 2021
Book

This book provides a thorough overview of the state-of-the-art FPGA-based robotic computing accelerator designs and summarizes their adopted optimized techniques. This book consists of ten chapters, delving into the details of how FPGAs have been utilized in robotic perception, localization, planning, and multi-robot collaboration tasks. In addition to individual robotic tasks, this book provides detailed descriptions of how FPGAs have been used in robotic products, including commercial autonomous vehicles and space exploration robots. Some key observations of this book has been published as a survey paper in IEEE Circuits and Systems Magazine, 2021.

Machine Learning Systems with TinyML
Vijay Janapa Reddi, Matthew Stewart, Ikechukwu Uchendu, Itai Shapira, Marcelo Rovai, Jayson Lin, Jeffrey Ma, Korneel Van den Berghe, Zishen Wan, Srivatsan Krishnan, Shvetank Prakash, Mark Mazumder, Colby Banbury, Jason Yik, Jessica Quaye, ... (contributor list)
Book / Github

This book is your gateway to the fast-paced world of AI systems through the lens of TinyML. This book aims to demystify the process of developing complete ML systems suitable for deployment - spanning key phases like data collection, model design, optimization, acceleration, security hardening, and integration. Crucial systems considerations like reliability, privacy, responsible AI, and solution validation are also explored in depth. This book is led by Prof. Vijay Janapa Reddi and resonates with Harvard TinyML course. Join us in this open-source collective effort - by the community, with the community, for the community.

PrePrint
Intelligence in Robotic Computing: Agile Design Flows for Building Efficient and Resilient Autonomous Machines
Zishen Wan, Vijay Janapa Reddi, Arijit Raychowdhury
ACM Student Research Competition (SRC), Grand Final, 2023
First Place, ACM/SIGBED Student Research Competition (SRC)
Paper / Media / Media

This report summarizes our recent efforts in facilitating the development of scalable, efficient, adaptive, and reliable autonomous machine computing, including automatic domain-specific SoC exploration, software-hardware co-design, and performance-efficiency-resilience co-optimization.

Publications       (*: Equal Contributions)
The Vulnerability-Adaptive Protection Paradigm Toward Reliable Autonomous Machines
Zishen Wan*, Yiming Gan*, Bo Yu, Shaoshan Liu, Arijit Raychowdhury, Yuhao Zhu
Communications of the ACM (CACM), 2024
Paper (to appear)

We characterize the inherent resilience of different compute kernels in autonomous vehicles and drones systems. We analyze the protection design landscape and propose the lightweight Vulnerable-Adaptive Protection (VAP) paradigm for resilient autonomous machines.

Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference
Akshat Ramachandran, Zishen Wan, Geonhwa Jeong, John Gustafson, Tushar Krishna
ACM/IEEE Design Automation Conference (DAC), 2024
Paper (to appear)

We present Logarithmic Posit, an adaptive and hardware-friendly datatype that dynamically adapts to DNN weight/activation distributions for efficient inference. We develop Logarithmic Posit quantization and Logarithmic Posit accelerator architecture via algorithm-hardware co-design.

RobotPerf: An Open-Source, Vendor-Agnostic, Benchmarking Suite for Evaluating Robotics Computing System Performance
Victor Mayoral-Vilches, Jason Jabbour, Yu-Shun Hsiao, Zishen Wan, Alejandra Martinez-Farina, Martino Crespo-Alvarez, Matthew Stewart, Juan Manuel Reina-Munoz, Prateek Nagras, Gaurav Vikhe, Mohammad Bakhshalipour, Martin Pinzger, Stefan Rass, Smruti Panigrahi, Giulio Corradi, Niladri Roy, Phillip B. Gibbons, Sabrina M. Neuman, Brian Plancher, Vijay Janapa Reddi
IEEE International Conference on Robotics and Automation (ICRA), 2024
Best Paper Award, IROS Robotics Benchmarking Workshop 2023
Paper / Poster / Code / Project Page / Media

We introduce RobotPerf, a benchmarking suite to evaluate robotics computing performance across a diverse range of hardware platforms. As an open-source initiative, RobotPerf remains committed to evolving with community input to advance the future of hardware-accelerated robotics.

MulBERRY: Enabling Bit-Error Robustness for Energy-Efficient Multi-Agent Autonomous Systems
Zishen Wan, Nandhini Chandramoorthy, Karthik Swaminathan, Pin-Yu Chen, Kshitij Bhardwaj, Vijay Janapa Reddi, Arijit Raychowdhury
ACM Inter Conf on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2024
Best Poster Award, IBM IEEE AI Compute Symposium 2023
Paper (to appear) / Media

We propose MulBERRY, a multi-agent robust learning framework to enhance bit error robustness and energy efficiency for autonomous swarm systems.

ORIANNA: An Accelerator Generation Framework for Optimization-Based Robotic Applications
Yuhui Hao, Yiming Gan, Bo Yu, Qiang Liu, Yinhe Han, Zishen Wan, Shaoshan Liu
ACM Inter Conf on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2024
Paper (to appear)

We propose ORIANNA, a framework leverageing a common abstraction factor graph to generate accelerators for diverse robotic applications (e.g., manipulators, vehicles, drones) containing multiple optimization-based algorithms (e.g., localization, planning).

H3DFACT: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations
Zishen Wan*, Che-Kai Liu*, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna, Arijit Raychowdhury
Design, Automation and Test in Europe Conference (DATE), 2024
Paper (to appear)

We present H3DFACT, the first heterogeneous 3D integrated in-memory compute engine capable of efficiently factorizing high-dimensional holographic representations towards next-generative cognitive AI.

Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs
Yu-Shun Hsiao*, Zishen Wan*, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023
Paper / Code

We introduce ROSFI, the first Robot Operating System (ROS) resilience analysis methodology, to assess the effect of silent data corruption (SDC) on safety-critical applications.

SEE-MCAM: Scalable Multi-bit FeFET Content Addressable Memories for Energy Efficient Associative Search
Shengxi Shou, Che-Kai Liu, Sanggeon Yun, Zishen Wan, Kai Ni, Mohsen Imani, X. Sharon Hu, Jianyi Yang, Cheng Zhuo, Xunzhao Yin
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2023
Paper / Media

We propose a scalable and compact multi-bit CAM designs with FeFET, and demonstrate speedup and energy efficiency improvement in hyperdimensional computing (HDC) applications.

A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking
Ashwin Lele*, Muya Chang*, Samuel Spetalnick, Brian Crafton, Shota Konna, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-der Chih, Meng-Fan Chang, Arijit Raychowdhury
IEEE Journal of Solid-State Circuits (JSSC), 2023
Paper

We present a heterogeneous programmable ARM Cortex-based SoC with power-efficient RRAM compute-in-memory for CNN and high-speed SRAM compute-near-memory for SNN for the modality-matched acceleration of the hybrid vision.

BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems
Zishen Wan, Nandhini Chandramoorthy, Karthik Swaminathan, Pin-Yu Chen, Vijay Janapa Reddi, Arijit Raychowdhury
ACM/IEEE Design Automation Conference (DAC), 2023
Paper / Slide / Poster

We propose BEERY, a robust learning framework to improve bit error robustness and energy efficiency for RL autonomous systems. BEERY enables robust low-voltage operation on UAVs, leading to high energy savings in both compute-level operation and system-level quality-of-flight.

MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles
Yu-Shun Hsiao*, Zishen Wan*, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi
Design, Automation and Test in Europe Conference (DATE), 2023
Paper / Slide / Poster / Code

We build a ROS-based end-to-end fault analysis framework to understand the resilience of Micro Aerial Vehicles (MAVs) system, and propose two low overhead anomaly-based transient fault detection and recovery schemes.

Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving
Kshitij Bhardwaj, Zishen Wan, Arijit Raychowdhury, Ryan Goldhahn
Design, Automation and Test in Europe Conference (DATE), 2023
Paper

We propose a lightweight, fully unsupervised and real-time adaptation algorithm for safety-critical lane detection of autonomous driving, and demonstrate its state-of-the-art performance on Nvidia Jetson Orin.

A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking
Muya Chang*, Ashwin Lele*, Samuel Spetalnick, Brian Crafton, Shota Konna, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-der Chih, Meng-Fan Chang, Arijit Raychowdhury
IEEE International Solid-State Circuits Conference (ISSCC), 2023
Paper

We propose a fully-programmable heterogeneous ARM Cortex-based SoC with an in-memory low-power RRAM-based CNN and a near-memory high-speed SRAM-based SNN in a hybrid architecture, for high-speed target identification and tracking applications.

Analyzing and Improving Resilience and Robustness of Autonomous Systems
Zishen Wan, Karthik Swaminathan, Pin-Yu Chen, Nandhini Chandramoorthy, Arijit Raychowdhury
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022
Paper / Media

We explore the various originations of fault sources across the computing stack of autonomous systems, and discuss the diverse fault impacts and fault mitigation techniques of different scales of autonomous systems.

Automatic Domain-Specific SoC Design for Autonomous Unmanned Aerial Vehicles
Srivatsan Krishnan, Zishen Wan, Kshitij Bhardwaj, Paul Whatmough, Aleksandra Faust, Sabrina M. Neuman, Gu-Yeon Wei, David Brooks, Vijay Janapa Reddi
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022
IEEE Micro Top Picks 2023 Honorable Mention
Paper / arXiv

We propose a machine learning-based design space exploration framework, Autopilot, that can automate the full system cyber-physical co-design for aerial robots. AutoPilot consistently outperforms general-purpose processors and specialized accelerators built for drones.

Improving Compute In-Memory ECC Reliability with Successive Correction
Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
ACM/IEEE Design Automation Conference (DAC), 2022
Paper / Video / Media

We propose a new ECC scheme for hard and soft errors in foundry RRAM-based Compute-In-Memory chip. We demonstrate single, double, and triple error correction offering up to 16,000× reduction in bit error rate, while consuming only 29.1% area and 26.3% power overhead.

Robotic Computing on FPGAs: Current Progress, Research Challenges, and Opportunities
Zishen Wan, Ashwin Lele, Bo Yu, Shaoshan Liu, Yu Wang, Vijay Janapa Reddi, Cong (Callie) Hao, Arijit Raychowdhury
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022
Paper / Slide / Video

We present the cross-layer robotic computing stack, illustrate the current progress and key design techniques. We summarize and highlight the challenges, research opportunities, and roadmap for the next-generation FPGA-based robotic computing systems.

An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems
Qiang Liu*, Zishen Wan*, Bo Yu*, Weizhuang Liu, Shaoshan Liu, Arijit Raychowdhury
IEEE Custom Integrated Circuits Conference (CICC), 2022
Paper / Slide

We present an energy-efficient and runtime-reconfigurable FPGA-based accelerator for robotic localization tasks. We exploit SLAM-specific data locality, sparsity, reuse, and parallelism, and achieve >5x performance improvement over state-of-the-art.

Roofline Model for UAVs: A Bottleneck Analysis Tool for Onboard Compute Characterization of Autonomous Unmanned Aerial Vehicles
Srivatsan Krishnan, Zishen Wan, Kshitij Bhardwaj, Ninad Jadhav, Aleksandra Faust, Vijay Janapa Reddi
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2022
Paper / Skyline Tool

We present a bottleneck analysis tool, Skyline, for designing compute systems for autonomous Unmanned Aerial Vehicles (UAV). The tool provides insights by exploiting the fundamental relationships between various components in the autonomous UAV such as sensor, compute, body dynamics.

FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems
Zishen Wan, Aqeel Anwar, Abdulrahman Mahmoud, Tianyu Jia, Yu-Shun Hsiao, Vijay Janapa Reddi, Arijit Raychowdhury
Design, Automation and Test in Europe Conference (DATE), 2022
Paper / Slide

We characterize the hardware transient fault impact on federated reinforcement learning system, a swarm intelligence paradigm in autonomous machines. We further propose application-aware cost-effective fault detection and mitigation scheme to enable autonomy reliability.

Circuit and System Technologies for Energy-Efficient Edge Robotics
Zishen Wan, Ashwin Lele, Arijit Raychowdhury
Asia and South Pacific Design Automation Conference (ASP-DAC), 2022 (Invited Paper)
Paper / Slide

We present a series of ultra-low-power accelerator and system designs on enabling the intelligence in edge robotic platforms, with an emphasis on mixed-signal circuit, neuro-inspired computing, benchmarking, software infrastructure, and algorithm-hardware co-design.

(Gif source: Google)
QuaRL: Quantization for Fast and Environmentally Sustainable Reinforcement Learning
Srivatsan Krishnan*, Max Lam*, Sharad Chitlangian*, Zishen Wan, Gabriel Barth-Maron, Aleksandra Faust, Vijay Janapa Reddi
Transactions on Machine Learning Research (TMLR), 2022
Paper / Google AI Blog

We propose a quantized distributed reinforcement learning (RL) training system, and enable more environmentally friendly RL by achieving carbon emission improvements between 1.9 × and 3.76× compared to training RL-agents in full-precision.

Analyzing and Improving Fault Tolerance of Learning-Based Navigation System
Zishen Wan, Aqeel Anwar, Yu-Shun Hsiao, Tianyu Jia, Vijay Janapa Reddi, Arijit Raychowdhury
ACM/IEEE Design Automation Conference (DAC), 2021
Best Presentation Award as DAC Young Fellow
Paper / Slide / Video / Media

We evaluate the resilience of learning-based navigation systems to transient and permanent hardware faults. We further propose two efficient fault mitigation techniques for both RL training and inference.

AutoSoC: Automating Algorithm-SoC Co-design for Aerial Robots
Srivatsan Krishnan, Thierry Tambe, Zishen Wan, Vijay Janapa Reddi
Pre-print, 2021
Paper / Poster

We present AutoSoC, a algorithms-hardware co-design framework for end-to-end learning-based aerial autonomous machines. AutoSoC runs the ASIC flow of place and route and generates layouts of the floor-planed accelerators with varying performance, area, and power consumption.

A Survey of FPGA-Based Robotic Computing
Zishen Wan*, Bo Yu*, Thomas Yuang Li, Jie Tang, Yuhao Zhu, Yu Wang, Arijit Raychowdhury, Shaoshan Liu
IEEE Circuits and Systems Magazine (CAS-M), 2021
Paper

We provide an overview of recent work on FPGA-based robotic accelerators. An analysis of software and hardware optimization techniques and main technical issues is presented, along with some commercial and space applications.

An Energy-Efficient Quad-Camera Visual System for Autonomous Machines on FPGA Platform
Zishen Wan*, Yuyang Zhang*, Arijit Raychowdhury, Bo Yu, Yanjun Zhang, Shaoshan Liu
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021
Paper / Slide / Summary Video / Long Video

We present a real-time and energy-efficient ORB (Oriented-Fast and Rotated-BRIEF) based visual system on FPGAs. Compared to Nvidia TX1 and Intel i7 CPU, our FPGA-based implementation achieves 5.6x and 3.4x speedup, as well as 3.0x and 34.6x power reduction, respectively.

iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform
Tian Gao*, Zishen Wan*, Yuyang Zhang, Bo Yu, Yanjun Zhang, Shaoshan Liu, Arijit Raychowdhury
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021
Paper

We present an energy-efficient hardware architecture for real-time ELAS (Efficient Large-scale Stereo) based stereo matching on FPGAs. Compared to SOTA SoC and Intel i7 CPU, our FPGA design achieves 3.32x and 38.4x speedup, and 1.13x and 27.1x power reduction, respectively.

Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference
Thierry Tambe, En-Yu Yang, Zishen Wan, Yuntian Deng, Vijay Janapa Reddi, Alexander Rush, David Brooks, Gu-Yeon Wei
ACM/IEEE Design Automation Conference (DAC), 2020
Best Paper Award
ACM SIGDA Research Highlights Nominee
Paper / arXiv (long version) / Media

We present an algorithm-hardware co-design centered around a novel floating-point inspired number format, which can achieve higher inference accuracies and lower per-operation energy compared to NVDLA-like PE.

The Sky Is Not the Limit: A Visual Performance Model for Cyber-Physical Co-Design in Autonomous Machines
Srivatsan Krishnan, Zishen Wan, Kshitij Bhardwaj, Paul Whatmough, Aleksandra Faust, Gu-Yeon Wei, David Brooks, Vijay Janapa Reddi
IEEE Computer Architecture Letters (CAL), 2020
Best Paper Award
Presented at International Symposium on High-Performance Computer Architecture (HPCA), 2021
Paper / Tool Website

We introduce a roofline-like model to understand the role of computing in aerial autonomous machines. The model provides insights by exploiting the fundamental relationships between various components in an aerial robot, such as sensor framerate, compute performance, and body dynamics.

Workshop Papers
Towards Cognitive AI Systems: a Survey and Prospective on Neuro-Symbolic AI
Zishen Wan, Che-Kai Liu, Hanchen Yang, Chaojian Li, Haoran You, Yonggan Fu, Cheng Wan, Tushar Krishna, Yingyan (Celine) Lin, Arijit Raychowdhury
Workshop on Systems for Next-Gen AI Paradigms, Conference on Machine Learning and Systems (MLSys) , 2023
Paper / Slide / Poster

We provide a systematic review of recent progress in neuro-symbolic AI (NSAI) and analyze the performance characteristics and computational operators of NSAI models. We discuss the challenges and potential future directions of NSAI from system and architectural perspectives.

VPP: The Vulnerability-Proportional Protection Paradigm Towards Reliable Autonomous Machines
Zishen Wan*, Yiming Gan*, Bo Yu, Shaoshan Liu, Arijit Raychowdhury, Yuhao Zhu
5th Workshop on Domain Specific System Architecture (DOSSA-5), International Symposium on Computer Architecture (ISCA) , 2023
Paper / Slide / Media

We characterize the inherent robustenss and performance of various autonomous machine computing kernels, and propose a Vulnerable-Proportional Protection (VPP) design paradigm to provide high protection coverage while introducing little cost.

Multi-Task Federated Reinforcement Learning with Adversaries
Aqeel Anwar, Zishen Wan, Arijit Raychowdhury
1st Adversarial Machine Learning Workshop, International Conference on Machine Learning (ICML), 2022
Paper

We analyze the multi-task federated reinforcement learning (MT-FedRL) algorithm with an adversarial perspective. We propose an effective adversarial attack method, and an adaptative detection and recovery scheme for MT-FedRL system.

RRAM-ECC: Improving Reliability of RRAM-Based Compute In-Memory
Zishen Wan*, Brian Crafton*, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury
13th Annual Non-Volatile Memories Workshop (NVMW) , 2022
Paper / Slide / Summary Video / Long Video

We explore the impact of device variation (calibrated with measured data on foundry RRAM arrays) and propose a new class of ECC for hard and soft errors in RRAM-based in-memory coomputing. We demonstrate the single, double, and triple error correction.

ActorQ: Quantization for Actor-Learner Distributed Reinforcement Learning
Max Lam*, Sharad Chitlangian*, Srivatsan Krishnan*, Zishen Wan, Gabriel Barth-Maron, Aleksandra Faust, Vijay Janapa Reddi
Hardware Aware Efficient Training (HEAT) Workshop, International Conference on Learning Representations (ICLR), 2021
Paper / Poster / Code

We introduce a novel Reinforcement Learning training paradigm, ActorQ, to speed up actor-learner distributed RL training. ActorQ demonstrates >1.5x-2.5× speedup, and faster convergence over full precision training on a range of tasks (Deepmind Control Suite) and RL algorithms (D4PG, DQN).

Quantized Reinforcement Learning (QuaRL)
Srivatsan Krishnan*, Sharad Chitlangian*, Max Lam*, Zishen Wan, Aleksandra Faust, Vijay Janapa Reddi
Resource-Constrained Machine Learning (ReCoML) Workshop, Conference on Machine Learning and System (MLSys), 2020
Paper / Code

We conduct the first comprehensive empirical study that quantifies the effects of quantization on various deep RL tasks and algorithms. We deploy a quantized RL-based robot navigation policy onto an embedded system, achieving 18x speedup and 4x reduction in memory usage.

Honors and Awards
  • 2024 ISSCC Student Travel Award
  • 2023 Best Poster Award, IBM IEEE AI Compute Symposium
  • 2023 Best Paper Award, Robotics Benchmarking Workshop, IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)
  • 2023 ML and Systems Rising Star
  • 2023 ISCA Student Travel Award
  • 2023 MLSys Student Travel Award
  • 2023 Roger P. Webb Graduate Research Assistant Excellence Award, Georgia Tech
  • 2023 IEEE Micro Top Picks, Honorable Mention ("in recognition of the most significant research papers in computer architecture")
  • 2022 1st Place, ACM/SIGBED Student Research Competition
  • 2022 3rd Place, ACM/SIGDA Student Research Competition (declined)
  • 2022 Qualcomm Fellowship
  • 2022 Young Fellow, IEEE/ACM Design Automation Conference (DAC)
  • 2022 CRNCH PhD Fellowship, Center for Research into Novel Computing Hierarchies, Georgia Tech
  • 2021 ACM SIGDA Research Highlights Nominee
  • 2021 Young Fellow, IEEE/ACM Design Automation Conference (DAC)
  • 2021 Best Presentation Award, Young Fellow Program at IEEE/ACM Design Automation Conference (DAC)
  • 2020 Best Paper Award, IEEE/ACM Design Automation Conference (DAC)
  • 2020 Best Paper Award, IEEE Computer Architecture Letters (CAL)
  • 2018 Chiang Chen Overseas Graduate Scholarship (10 of all undergraduates and graduates in China)
  • 2018 Best Undergraduate Thesis Award
  • 2018 Frist Place, Chunhui Innovation Achievement Award (Highest Student Academic Honor of HIT)
  • 2018 Top Ten Outstanding Undergraduates of HIT
  • 2018 China Telecom Scholarship
  • 2017 Innovation and Entrepreneurship Award, Ministry of Industry and Information, China
  • 2016 First Place, National Mathematical Contest in Modeling, China
  • 2016 Siemens Acedemic Scholarship
  • 2015 Johnson Electric Acedemic Scholarship
  • Talks

    • "Co-Design of NeuroSymbolic Cognitive AI Systems"
    • - 09/2023 Guest Lecture, EE6900 Neuromorphic Computing (Host: Prof. Yan Fang), Atlanta, GA
      - 05/2023 Georgia Tech 3D Systems Packaging Research Center Spring Meeting, Atlanta, GA
      - 05/2023 CoCoSys (Center for the Co-Design of Cognitive Systems) Annual Summit, DARPA SRC JUMP 2.0, Atlanta, GA
    • "Intelligence in Robotic Computing: Exploring Agile Design Flows for Efficient and Resilient Autonomous Systems"
    • - 02/2024 CRIDC (Career, Research, and Innovation Development Conference), Atlanta, GA
      - 11/2023 6th IBM AI Compute Symposium, IBM T.J. Watson Research Center, Yorktown Heights, NY
      - 09/2023 Georgia Tech Computer Architecture Research Seminar (Arch-Whisky ), Atlanta, GA
      - 08/2023 ML and Systems Rising Stars Workshop, Google, Mountain View, CA
      - 05/2023 Georgia Tech Chips Day, Atlanta, GA
      - 03/2023 Georgia Tech EIC Lab (Host: Prof. Celine Lin), Atlanta, GA
      - 02/2023 CRNCH (Center for Research into Novel Computing Hierarchies) Annual Summit, Atlanta, GA
      - 11/2022 ACM Student Research Competition at ICCAD, San Diego, CA
    • "Efficient Algorithm-Hardware Co-Design for Autonomous Machine Computing"
    • - 02/2023 CRIDC (Career, Research, and Innovation Development Conference), Atlanta, GA
      - 10/2022 5th IBM AI Compute Symposium, IBM T.J. Watson Research Center, Yorktown Heights, NY
      - 10/2022 CBRIC (Research Center for Brain-Inspired Computing) Annual Summit, DARPA JUMP SRC, Purdue University, IN
      - 03/2022 Guest Lecture, Georgia Tech ECE8893 Parallel Programming for FPGAs (Host: Prof. Callie Hao), Atlanta, GA
      - 02/2022 CRNCH (Center for Research into Novel Computing Hierarchies) Annual Summit, Online
    • "Enabling Reliable and Safe Autonomous Systems"
    • - 02/2024 CRNCH (Center for Research into Novel Computing Hierarchies) Annual Summit, Atlanta, GA
      - 05/2023 CoCoSys (Center for the Co-Design of Cognitive Systems) Annual Summit, DARPA SRC JUMP 2.0, Atlanta, GA
      - 11/2022 ACM Student Research Competition at ESWEEK, Online
      - 06/2022 COMPSAC plenary panel 'Reliability of Autonomous Machines', Online
      - 10/2021 CBRIC (Center for Brain-Inspired Computing) Annual Summit, DARPA JUMP SRC, Online
      - 08/2021 CBRIC (Center for Brain-Inspired Computing) Industry Talk, DARPA JUMP SRC, Online
      - 07/2020 Harvard Architecture, Circuits and Compilers Lab, Online
    • "Edge Computing on Aerial Robots"
    • - 11/2021 ACM Student Research Competition at ICCAD, Online
      - 09/2020 Georgia Tech Integrated Circuits and System Research Lab, Online
    Academic Service

    • Conference Reviewer: CAV@ASPLOS'24, DAC'24, DAC'23, ESWEEK'23, IJCAI'23, NPC'22.
    • Journal Reviewer: IEEE JSSC, IEEE TCAD, IEEE TCAS-I, IEEE TBioCAS, IEEE Micro, IEEE TIM, ACM JATS.
    • Artifact Evaluation Committee: ISCA'24, MICRO'23, ISCA'23, ASPLOS'23, MICRO'22, ASPLOS'22, IISWC'22.
    • Working Group: Co-found MLCommons (MLPerf) Resilience and Robustness Research Working Group.
    • Panelist: COMPSAC'22.
    • Outreach activity: ISSCC'24 News and Media Team, Steering Committee of IEEE Entrepreneurship China, IISWC'19 Volunteer.
    Misc

    • Sports: I like table tennis, soccer, swimming, hiking, and jogging. I'm a member of Georgia Tech Table Tennis Association.
    • Arts: I like calligraphy and have practiced more than 10 years. My undergrad Calculus class notes was awarded 'The Most Beautiful Class Note' and permanently collected and displayed by university museum.

    Last Update: Feb. 2024

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