Zishen Wan  

I am a 5th-year Ph.D. student at Georgia Tech, advised by Prof. Arijit Raychowdhury and Prof. Tushar Krishna. I also closely work with Prof. Vijay Janapa Reddi. My research interests are in computer architecture and VLSI, with a focus on designing efficient and reliable hardware and systems for autonomous machines and cognitive intelligence.

I received M.S. from Harvard University where I was advised by Prof. Vijay Janapa Reddi, and collaborated with Prof. David Brooks and Prof. Gu-Yeon Wei. I received B.Eng. from Harbin Institute of Technology. I was a visiting student at MIT CSAIL, National Chiao Tung University, and National Tsing Hua University.

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• System:
  
  • Resilient and Efficient Autonomous Machine Computing: [ASPLOS'24a] [CACM'24] [TCAD'23] [DAC'23] [ISCA'23(W)] [DATE'23a] [DATE'23b] [ISPASS'22] [ICCAD'22] [DATE'22] [ICML'22(W)] [DAC'21] [CAL'20]
  • Co-Design for Edge Intelligence and Efficient AI: [Book - TinyML] [DAC'24] [ICLR'24(W)] [TMLR'22] [ICLR'21(W)] [DAC'20] [MLSys'20(W)]
    
• Architecture:
  
  • Domain-Specific Architecture for Autonomous Machines: [Book - Synthesis Lectures on Computer Architecture] [ASPLOS'24b] [ICRA'24] [MICRO'22] [CICC'22] [AICAS'22] [ASP-DAC'22] [CAS-M'21] [AICAS'21]
  • Neuro-Symbolic and Embodied AI: [ICCAD'24] [ESWEEK'24]] [TCASAI'24]] [ISPASS'24] [DATE'24] [MLSys'23(W)]
• Circuit & Technology:
  
  • In-Memory Computing and Non-Volatile Memory: [JATS'24] [ICCAD'23] [JSSC'23] [ISSCC'23] [DAC'22] [NVM'22(W)]

This book provides a thorough overview of the state-of-the-art FPGA-based robotic computing accelerator designs and summarizes their adopted optimized techniques. This book consists of ten chapters, delving into the details of how FPGAs have been utilized in robotic perception, localization, planning, and multi-robot collaboration tasks. In addition to individual robotic tasks, this book provides detailed descriptions of how FPGAs have been used in robotic products, including commercial autonomous vehicles and space exploration robots. Some key observations of this book has been published as a survey paper in IEEE Circuits and Systems Magazine, 2021.

This book is your gateway to the fast-paced world of AI systems through the lens of TinyML. This book aims to demystify the process of developing complete ML systems suitable for deployment - spanning key phases like data collection, model design, optimization, acceleration, security hardening, and integration. Crucial systems considerations like reliability, privacy, responsible AI, and solution validation are also explored in depth. This book is led by Prof. Vijay Janapa Reddi and resonates with Harvard TinyML course. Join us in this open-source collective effort - by the community, with the community, for the community.

This report summarizes our recent efforts in facilitating the development of scalable, efficient, adaptive, and reliable autonomous machine computing, including automatic domain-specific SoC exploration, software-hardware co-design, and performance-efficiency-resilience co-optimization.

We analyze the neuro-symbolic workload chracteristics, and present a hardware acceleration case study for vector-symbolic architecture to improve the performance, efficiency, and scalability of neuro-symbolic computing.

We present a cognitive-inspired modular framework for cooperative embodied AI systems and identify the system inherent characteristics and optimization opportunities. Evaluated on long-horizon multi-objective tasks, our cross-layer optimization achieves an average 3.93x speedup in end-to-end task execution.

We systematically categorize neuro-symbolic AI workloads, conduct workload characterizations across hardware platforms, and identify cross-layer optimization opportunites for neuro-symbolic systems.

We characterize the inherent resilience of different compute kernels in autonomous vehicles and drones systems. We analyze the protection design landscape and propose the lightweight Vulnerable-Adaptive Protection (VAP) paradigm for resilient autonomous machines.

We present Logarithmic Posit, an adaptive and hardware-friendly datatype that dynamically adapts to DNN weight/activation distributions for efficient inference. We develop Logarithmic Posit quantization and Logarithmic Posit accelerator architecture via algorithm-hardware co-design.

We propose MulBERRY, a multi-agent robust learning framework to enhance bit error robustness and energy efficiency for autonomous swarm systems.

We propose ORIANNA, a framework leverageing a common abstraction factor graph to generate accelerators for diverse robotic applications (e.g., manipulators, vehicles, drones) containing multiple optimization-based algorithms (e.g., localization, planning).

We introduce RobotPerf, a benchmarking suite to evaluate robotics computing performance across a diverse range of hardware platforms. As an open-source initiative, RobotPerf remains committed to evolving with community input to advance the future of hardware-accelerated robotics.

We present H3DFACT, the first heterogeneous 3D integrated in-memory compute engine capable of efficiently factorizing high-dimensional holographic representations towards next-generative cognitive AI.

We analyze the computational chanllenges of integrating LLMs and neuro-symbolic architecture, and explore state-of-the-art solutions, focusing on the memory-centric computing principles at both algorithmic and hardware levels.

We present a benchmarking framework and conduct a comprehensive measurement study of prediction-time DNN adaptation techniques, encompassing both supervised and unsupervised approaches, on CIM hardware substrates at the edge.

We introduce ROSFI, the first Robot Operating System (ROS) resilience analysis methodology, to assess the effect of silent data corruption (SDC) on safety-critical applications.

We propose a scalable and compact multi-bit CAM designs with FeFET, and demonstrate speedup and energy efficiency improvement in hyperdimensional computing (HDC) applications.

We present a heterogeneous programmable ARM Cortex-based SoC with power-efficient RRAM compute-in-memory for CNN and high-speed SRAM compute-near-memory for SNN for the modality-matched acceleration of the hybrid vision.

We propose BEERY, a robust learning framework to improve bit error robustness and energy efficiency for RL autonomous systems. BEERY enables robust low-voltage operation on UAVs, leading to high energy savings in both compute-level operation and system-level quality-of-flight.

We build a ROS-based end-to-end fault analysis framework to understand the resilience of Micro Aerial Vehicles (MAVs) system, and propose two low overhead anomaly-based transient fault detection and recovery schemes.

We propose a lightweight, fully unsupervised and real-time adaptation algorithm for safety-critical lane detection of autonomous driving, and demonstrate its state-of-the-art performance on Nvidia Jetson Orin.

We propose a fully-programmable heterogeneous ARM Cortex-based SoC with an in-memory low-power RRAM-based CNN and a near-memory high-speed SRAM-based SNN in a hybrid architecture, for high-speed target identification and tracking applications.

We explore the various originations of fault sources across the computing stack of autonomous systems, and discuss the diverse fault impacts and fault mitigation techniques of different scales of autonomous systems.

We propose a machine learning-based design space exploration framework, Autopilot, that can automate the full system cyber-physical co-design for aerial robots. AutoPilot consistently outperforms general-purpose processors and specialized accelerators built for drones.

We propose a new ECC scheme for hard and soft errors in foundry RRAM-based Compute-In-Memory chip. We demonstrate single, double, and triple error correction offering up to 16,000× reduction in bit error rate, while consuming only 29.1% area and 26.3% power overhead.

We present the cross-layer robotic computing stack, illustrate the current progress and key design techniques. We summarize and highlight the challenges, research opportunities, and roadmap for the next-generation FPGA-based robotic computing systems.

We present an energy-efficient and runtime-reconfigurable FPGA-based accelerator for robotic localization tasks. We exploit SLAM-specific data locality, sparsity, reuse, and parallelism, and achieve >5x performance improvement over state-of-the-art.

We present a bottleneck analysis tool, Skyline, for designing compute systems for autonomous Unmanned Aerial Vehicles (UAV). The tool provides insights by exploiting the fundamental relationships between various components in the autonomous UAV such as sensor, compute, body dynamics.

We characterize the hardware transient fault impact on federated reinforcement learning system, a swarm intelligence paradigm in autonomous machines. We further propose application-aware cost-effective fault detection and mitigation scheme to enable autonomy reliability.

We present a series of ultra-low-power accelerator and system designs on enabling the intelligence in edge robotic platforms, with an emphasis on mixed-signal circuit, neuro-inspired computing, benchmarking, software infrastructure, and algorithm-hardware co-design.

We propose a quantized distributed reinforcement learning (RL) training system, and enable more environmentally friendly RL by achieving carbon emission improvements between 1.9 × and 3.76× compared to training RL-agents in full-precision.

We evaluate the resilience of learning-based navigation systems to transient and permanent hardware faults. We further propose two efficient fault mitigation techniques for both RL training and inference.

We present AutoSoC, a algorithms-hardware co-design framework for end-to-end learning-based aerial autonomous machines. AutoSoC runs the ASIC flow of place and route and generates layouts of the floor-planed accelerators with varying performance, area, and power consumption.

We provide an overview of recent work on FPGA-based robotic accelerators. An analysis of software and hardware optimization techniques and main technical issues is presented, along with some commercial and space applications.

We present a real-time and energy-efficient ORB (Oriented-Fast and Rotated-BRIEF) based visual system on FPGAs. Compared to Nvidia TX1 and Intel i7 CPU, our FPGA-based implementation achieves 5.6x and 3.4x speedup, as well as 3.0x and 34.6x power reduction, respectively.

We present an energy-efficient hardware architecture for real-time ELAS (Efficient Large-scale Stereo) based stereo matching on FPGAs. Compared to SOTA SoC and Intel i7 CPU, our FPGA design achieves 3.32x and 38.4x speedup, and 1.13x and 27.1x power reduction, respectively.

We present an algorithm-hardware co-design centered around a novel floating-point inspired number format, which can achieve higher inference accuracies and lower per-operation energy compared to NVDLA-like PE.

We introduce a roofline-like model to understand the role of computing in aerial autonomous machines. The model provides insights by exploiting the fundamental relationships between various components in an aerial robot, such as sensor framerate, compute performance, and body dynamics.

We present a cognitive-inspired modular framework for cooperative embodied AI systems on long-horizon planning tasks. We identify the system inherent characteristics and optimization opportunities.

We present ResGNN, a GNN resilience characterization framework against hardware faults and attacks, including voltage scaling, transient faults, row-hammer attacks, etc. ResGNN unlocks the opportunity to understand GNN resilience and adaptive protection scheme, to achieve reliable and efficient GNN systems.

We derive scaling laws for adversarial robustness which can be extrapolated in the future to provide an estimate of how much cost we would need to pay to reach a desired level of robustness.

We provide a systematic review of recent progress in neuro-symbolic AI (NSAI) and analyze the performance characteristics and computational operators of NSAI models. We discuss the challenges and potential future directions of NSAI from system and architectural perspectives.

We characterize the inherent robustenss and performance of various autonomous machine computing kernels, and propose a Vulnerable-Proportional Protection (VPP) design paradigm to provide high protection coverage while introducing little cost.

We analyze the multi-task federated reinforcement learning (MT-FedRL) algorithm with an adversarial perspective. We propose an effective adversarial attack method, and an adaptative detection and recovery scheme for MT-FedRL system.

We explore the impact of device variation (calibrated with measured data on foundry RRAM arrays) and propose a new class of ECC for hard and soft errors in RRAM-based in-memory coomputing. We demonstrate the single, double, and triple error correction.

We introduce a novel Reinforcement Learning training paradigm, ActorQ, to speed up actor-learner distributed RL training. ActorQ demonstrates >1.5x-2.5× speedup, and faster convergence over full precision training on a range of tasks (Deepmind Control Suite) and RL algorithms (D4PG, DQN).

We conduct the first comprehensive empirical study that quantifies the effects of quantization on various deep RL tasks and algorithms. We deploy a quantized RL-based robot navigation policy onto an embedded system, achieving 18x speedup and 4x reduction in memory usage.

• "Co-Design of NeuroSymbolic Cognitive AI Systems"
- 08/2024 Invited Talk, University of Minnesota, Twin Cities (host: Prof. Katie Zhao), Minneapolis, MN
- 05/2024 Young Professional Symposium, Conference on Machine Learning and Systems (MLSys), Santa Clara, CA
- 05/2024 International Workshop on Neuro-symbolic Systems (NeuS), UC Berkeley, Berkeley, CA
- 03/2024 CoCoSys (Center for the Co-Design of Cognitive Systems) Annual Summit, DARPA SRC JUMP 2.0, Atlanta, GA
- 09/2023 Guest Lecture, EE6900 Neuromorphic Computing (Host: Prof. Yan Fang), Atlanta, GA
- 05/2023 Georgia Tech 3D Systems Packaging Research Center Spring Meeting, Atlanta, GA
- 05/2023 CoCoSys (Center for the Co-Design of Cognitive Systems) Annual Summit, DARPA SRC JUMP 2.0, Atlanta, GA

• "Towards Efficient and Resilient Autonomous Edge through Technology-System Co-Exploration"
- 08/2024 Invited Talk, Lawrence Livermore National Laboratory (host: Dr. Kshitij Bhardwaj), Livermore, CA

• "Intelligence in Robotic Computing: Exploring Agile Design Flows for Efficient and Resilient Autonomous Systems"
- 11/2024 Invited Talk, MICRO Workshop on Robotics Acceleration with Computing Hardware, Austin, TX
- 09/2024 ESWEEK (Embedded Systems Week) PhD Forum, Raleigh, NC
- 05/2024 Cyber-Physical System Rising Star Workshop, University of Virginia, Charlottesville, VA
- 05/2024 CoCoSys (Center for the Co-Design of Cognitive Systems) Liaison Meeting, DARPA SRC JUMP 2.0, Atlanta, GA
- 02/2024 CRIDC (Career, Research, and Innovation Development Conference), Atlanta, GA
- 02/2024 Georgia Tech Computer Architecture Research Seminar (Arch-Whisky), Atlanta, GA
- 11/2023 6th IBM AI Compute Symposium, IBM T.J. Watson Research Center, Yorktown Heights, NY
- 08/2023 ML and Systems Rising Stars Workshop, Google, Mountain View, CA
- 05/2023 Georgia Tech Chips Day, Atlanta, GA
- 03/2023 Georgia Tech EIC Lab (Host: Prof. Celine Lin), Atlanta, GA
- 02/2023 CRNCH (Center for Research into Novel Computing Hierarchies) Annual Summit, Atlanta, GA
- 11/2022 ACM Student Research Competition at ICCAD, San Diego, CA

• "Efficient Algorithm-Hardware Co-Design for Autonomous Machine Computing"
- 09/2023 Georgia Tech Computer Architecture Research Seminar (Arch-Whisky ), Atlanta, GA
- 02/2023 CRIDC (Career, Research, and Innovation Development Conference), Atlanta, GA
- 10/2022 5th IBM AI Compute Symposium, IBM T.J. Watson Research Center, Yorktown Heights, NY
- 10/2022 CBRIC (Research Center for Brain-Inspired Computing) Annual Summit, DARPA JUMP SRC, Purdue University, IN
- 03/2022 Guest Lecture, Georgia Tech ECE8893 Parallel Programming for FPGAs (Host: Prof. Callie Hao), Atlanta, GA
- 02/2022 CRNCH (Center for Research into Novel Computing Hierarchies) Annual Summit, Online
• "Enabling Reliable and Safe Autonomous Systems"
- 03/2024 CoCoSys (Center for the Co-Design of Cognitive Systems) Annual Summit, DARPA SRC JUMP 2.0, Atlanta, GA
- 02/2024 CRNCH (Center for Research into Novel Computing Hierarchies) Annual Summit, Atlanta, GA
- 05/2023 CoCoSys (Center for the Co-Design of Cognitive Systems) Annual Summit, DARPA SRC JUMP 2.0, Atlanta, GA
- 11/2022 ACM Student Research Competition at ESWEEK, Online
- 06/2022 COMPSAC plenary panel 'Reliability of Autonomous Machines', Online
- 10/2021 CBRIC (Center for Brain-Inspired Computing) Annual Summit, DARPA JUMP SRC, Online
- 08/2021 CBRIC (Center for Brain-Inspired Computing) Industry Talk, DARPA JUMP SRC, Online
- 07/2020 Harvard Architecture, Circuits and Compilers Lab, Online
• "Edge Computing on Aerial Robots"
- 11/2021 ACM Student Research Competition at ICCAD, Online
- 09/2020 Georgia Tech Integrated Circuits and System Research Lab, Online

• Conference Reviewer: CAV@ASPLOS'24, DAC'24, DAC'23, ESWEEK'23, IJCAI'23, NPC'22.
• Journal Reviewer: IEEE JSSC, IEEE TCAD, IEEE TCAS-I, IEEE TBioCAS, IEEE JETCAS, IEEE Micro, IEEE TIM, ACM JATS.
• Artifact Evaluation Committee: ISCA'24, MICRO'23, ISCA'23, ASPLOS'23, MICRO'22, ASPLOS'22, IISWC'22.
• Workshop & Special Session Oragnizer: ICCAD'24, ESWEEK'24.
• Working Group: Co-found MLCommons (MLPerf) Resilience and Robustness Research Working Group.
• Panelist: COMPSAC'22.
• Outreach activity: ISSCC'24 News and Media Team, Steering Committee of Computer Architecture Student Association (CASA), Steering Committee of IEEE Entrepreneurship China, IISWC'19 Volunteer.

• Sports: I like table tennis, soccer, swimming, hiking, and jogging. I'm a member of Georgia Tech Table Tennis Association.
• Arts: I like calligraphy and have practiced more than 10 years. My undergrad Calculus class notes was awarded 'The Most Beautiful Class Note' and permanently collected and displayed by Harbin Institute of Technology university museum.

Last Update: Nov. 2024

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